1. Field
Aspects of the present invention relate generally to interconnect structures for use in semiconductor devices and methods for forming such structures.
2. Description of the Related Art
Copper interconnects have become the industry standard since 180 nm CMOS technology nodes because of its high interconnect conductivity and electromigration resistance. However, comparing to other transition metals, copper has much higher diffusivity in silicon-based materials. The rapid diffusion of copper atoms into the surrounding silicon dioxide or other low-k dielectric materials during device operation creates shortcut paths that degrade the dielectric layer and result in device failure. Therefore, the dielectric reliability becomes one of the major concerns in copper interconnect structures. A current solution is to embed the copper interconnect into a tantalum nitride or a tantalum sidewall barrier and enclose the copper interconnect with a silicon-containing dielectric capping layer, such as silicon nitride or silicon carbide. The properties of the capping layer are especially critical since a common failure mechanism for electromigration is through the capping layer.
Making the capping layer thicker to prevent electromigration is not an effective solution as the dielectric constant of capping layer is highest in the metallization stack, which strongly impairs the effective dielectric constant of an interconnect level. Thus, the thickness of the capping layer must be minimized while still maintaining sufficient diffusion-blocking features and good adhesion strength with adjoining layers
Manufacturers of semiconductor devices are ever in pursuit of smaller geometries with increased capacity at less cost. As such, the dimensions of interconnect structures and their respective capping layers must be reduced as well. The thickness of silicon-containing dielectric capping layers, such as silicon nitride or silicon carbide layers, has been limited to about 20 nm because it is difficult to ensure the necessary diffusion-blocking properties at thicknesses less than 20 nm. Alternative approaches such as using a selective metal capping barrier or a copper silicon nitride buffer layer between the copper and silicon-containing dielectric capping layer have been proposed. However, such approaches are undesirable due to an increase in interconnect resistance, which reduces device performance.
Therefore, a need exists for improved interconnect structures and methods for forming such structures.